Besides that the package pin delays are on the order of 10's of ps, so they should be compensated for in the routing of the traces, which completely blows up the 0. Before selecting the high-speed PCB material for your fast PCB plan, it is essential to decide a worth (or qualities) for DK and Z0 for your transmission line (or lines). 77 2195. The propagation delay corresponding to the speed of light in vacuum is 84. Capacitance = ϵ ∗ Area/DielectricThickness C a p a c i t a n c e = ϵ ∗ A r e a / D i e l e c t r i c T h i c k n e s s. 6 and 6. H 1 H 1 = subtrate height 1. This capacitance is already included in the IC production trim for C L1 and C L2. . 8mm (0. These delay lines are available with or without. An interconnect trace on a board that is 12 inches long has a time delay of about 12 inches/6 in/nsec = 2 nsec. A picosecond is 1 x 10^-12 seconds. This is because the value of the trace resistance may lead to various design modifications and implementation issues. h = Height of Dielectric. 29 4 Feature-Specific Design Information. These include adherence to high speed layout guidelines in order to correctly route high speed and RF PCB trace lengths. Common-mode impedance occurs with the pair driven in parallel from a common-source. The main difference between these types of traces is their location in the PCB: microstrips are on the surface layer, while striplines are on an inner layer between two reference planes. Use the 'tline' element in LTSpice instead. 0 8 GT/s 23. As an example, assume DLY is 12 ps. The de-skew trombone on one of the P/N legs may have less delay per unit length compared to the straight trace on the other leg. 25GHz 20-inch line freq dB Layout. This stack-up assumes eUSB2 and USB differential microstrip routing on the outer layers. PCB Pre-Layout Simulation Phase 2. There are tables available that give approximate propogationn delays (PDs) dfor various PCB materials and track topology so you can start with a rough guess of. Insertion Loss. A rising edge with a risetime of 1ns would occupy a trace length of 1ns/(2*85ps) ~ 6in (~ 15cm). 8Figure is 1ns and the input source is 1V step with 1ns delay. Differential Pair Measurement Result xxx~xxx xxxΩ±xx%; Board Name xxxxxxxxxx Single End Spec. 77 nH per inch. e. 1mm ball pitch cutoff frequency is ~ 58GHz, 0. 3. 8mm (0. The flight time of a 16-in. Using 1/16 of wavelength as the "safe limit" below which we don't need to worry about reflections and relative signal timing, it'sMaximum Number of DDR SDRAM Interfaces Supported per FPGA 1. 031”) thick PCB (FR-4) has: ˜ 4nH and 0. – PCB traces have length • they must have delays – PCB traces distort the signal • delays may be longer than the simple flight. 192 mm gap shall be 100Ω ± 10%. Commonly fabricated with printed circuit board (PCB) technology, a microstrip antenna calculator tool is an electrical transmission line that is able to transmit RF signals. It is caused by velocity limitations in a physical. CLOCK SOURCE LOAD R = Z0 - Zc Zc = Clock Output Impedance RZ0. 015) , the loss is dominated by the square root function at low frequencies, then becomes dominated by the linear dielectric loss at higher frequencies, as seen in. The next equation shows the amount of inductance in microhenries for a component lead that has a diameter of 0. These traces could be one of the following: Multiple single-ended traces routed in parallel. Tpd is propagation delay and V (velocity) is the reciprocal of Tpd. We sometimes call the. A six-inch trace would then have a total propagation time of 6 × 150 = 900 ps . The four main ways to terminate a signal trace are shown below. Keep the spacing between the pair consistent. The matching requirements are dependent on the target data rate, FPGA, and memory device and must include both PCB trace delay and package delay. When designing high-speed boards, you need to worry about two things: length matching in parallel nets and differential pairs, and specified trace lengths to comply with specific routing standards. It is usually desired to have a measure of the trace/cable loss per unit length (per inch, meter, etc) so that the S-parameters for any required length can be created from the original measured. 8mm (0. There are many calculators available online, as well as built into your PCB design software. 51Propagation Delay is the length of time taken for a signal to reach its destination in printed circuit boards (PCBs). 36 RF / Microwave Design - Line Types and Impedance (Zo) Coplanar Waveguide)CPW Allows Variation of Trace. Open the PCB List Panel (Panels button, lower right of the Altium window). In lower speed or lower frequency devices,. The PCB shown in Figure 2 was design to evaluate the effects of only two corners per trace using various. where C 0 is in picofarads per inch, t PD is in picoseconds per inch, Z 0 is in ohms,. Timing Delay Measurement Result PCB Series No. Example 1: Must calculate the resistance of a 4 inch long and 12 mils width trace on a 70um copper PCB at 70 degrees celsius temperature. 0. 2. So the board thickness variation causes the calculated trace impedance to vary more than the wildly variable Er values that are commonly quoted. 39 nsec. Second choice: You can model a transmission line with a sequence of pi or T sections. Balancing FR4 dielectric constant with PCB laminate thickness and trace width is a difficult problem, but the right stackup manager can help you produce accurate impedance and propagation delay calculations. Other analog traces are used as delay lines and will meander a bit. As with any attenuation-due-to-metal calculation, microstrip attenuation can be expressed as a simple function of radio frequency resistance per meter R' and the line's characteristic impedance Z0, in either Nepers/meter or dB/meter:Traces electrically behave as transmission lines Crosstalk, attenuation, impedance mismatch are important Common rule of thumb for threshold associated with trace electrical length t d > t r /4 t d = line delay=delay/unit length*line length tr = 20% -. 16. You then subtract the PCB-trace delay of DATA1 from the total delay to get 3. For a square wave signal with a rise time of 1 ns, when the length of the pcb trace is 0. 3. Conductor loss in a PCB transmission line. 433: 107893,50. Then, just apply: Allowed_Length = Allowed_Delay/(140 ps/inch) where 140 ps/inch is typical for a microstrip on FR4. 8pF per cm er = PCB material ̃ 10nH and 2. Example 2: Must calculate the voltage drop of a 12 centimeters long and 1 millimeter width trace on a 35um copper PCB at 2 amperes and 50 degrees celsius temperature. Here, = resistivity at copper. Each dip in the TDR trace is the reflection from each corner. 6 × 10 9) ≈ 150 × 10-12 seconds per inch = 150ps per inch. 025 x 0. As the εr increases, the propagation delay (tPD) also increases. 9 160 0. (7038 ps/m or 7. For a PCB with a dielectric constant of 4 (like FR4 which is in the range of 3 to 5) the propagation delay doubles. Thickness: Thickness of the stripline conductor. This means we need the trace to be under 17. Figure 11 Sdd21 of 8 inch long PCB trace with varying intra-pair skew simulated using Keysight ADS. Detangling the hair of a 9-year old doesn’t take as long as routing PCB traces, but the results are just as painful if not done correctly. 33 ns /meter. 49 references 12. ±10%. 031”) thick PCB (FR-4) has: ˜ 4nH and 0. 3 Propagation (Trace) delay must be carefully evaluated and controlled for the respective groups. The trace delay is smaller in the via anti-pad area due to less coupling to the reference planes. The PCB vendors quote that they like traces down to 7 mil. GEG Calculators is a comprehensive online platform that offers a wide range of calculators to cater to various needs. In a PCB, the propagation delay experienced by a. Typical Delay Times for Various Types of Transmission LinesThese define the number of used test coupons with different trace lengths. You must optimize the PCB trace impedance to achieve a better return loss or less signal reflection. This tool calculates the time delay in inches per nanosecond. 25 to 0. 3 Printed Circuit Boards and Traces A quick review of PCB trace terminology is in order. For example, for FR4 material common practice is to use 150 ps/inch. 26 3. the market. 8mm (0. 8mm (0. The rule of thumb approximation is slightly higher than the actual value for 4 mils trace and a useful, easy to remember figure. If the distance is increased to 3m for. Component: Copper Traces Purpose: Interconnect two or more points Problem: Inductance and Capacitance x = length of trace (cm) w = width of trace (cm) h = height of trace (cm) t = thickness of trace (cm) e r = PCB Permeability 0. 44 x A0. The area of a PCB trace is the width multiplied. You still need to follow all the rules that would apply to digital logic speeds reaching over 100 MHz. 01 is. 5 ps/mm in air where the dielectric constant is 1. 5. So if you then need to do a, for example 100ps delay on a trace with a Tpd factor of 170ps/inch (a quite common PCB velocity factor) the trace would be ~590 mils in length. 0. Brad 165. Because both signals are differential, you can take the average of DDR_CK and DDR_CKn (or DDR_DQS and DDR_DQSn) and input the length (in inches) for each byte in each cell. Maximum current flow is going to be 12 Amps RMS. 10 All External Signals. The complicated structure of a PCB substrate can lead to resonances at lower frequencies, depending on the trace-to-glass-weave. Remember, 100+ MHz digital logic carries 1GHz components too, because square. Trace length matching. These standards must be followed if your PCB is to be compliant. 75 mm. The impedance of the traces were approximately 150 ohm, 130 ohms, and 110 ohms respectively. 92445. are simulated for with trace width W=4 mil and offset ranging from -12 to +12 mils and offset step 1 mil. Again, the lossless case is found by taking G = R = 0. Rule of Thumb #3 Signal speed on an interconnect. People use serpentine traces to delay signals, though I don't personally know of a case in the 1 GHz range. Communication signals operate at different frequencies, and you’re able to get the clock period by inverting the frequency value. 0 ns Output minimum delay = –t h of external register = –0. 2 Find the trace delay, or "DLY," in pico seconds or "ps" per inch. Figure 2 Test PCB and TDR response. Simulation shows the stray capacitance of the trace is about 1. It's an advanced topic. If you have an edge rate of 1ns and the copper trace is longer than 1 inch, you’ll need to take appropriate measures for impedance control. You must determine what this factor is for your PCB and then apply the conversion to the delay values that. PROP_DELAY 16281-005 Figure 5. ) •largely eliminates need for gate-level simulation to verify the delay of. 1. data rate approaches ~10 gigabits per second on traces with routing lengths often greater than 12 inches in today’sIPC-2152 Calculator. 0pF per inch Propagation delay refers to the inverse of the speed of a traveling electromagnetic signal. 10. The PCB traces act as transmission lines when the line delay is equal to or greater than 1/6 the rise (or fall) time. To ensure good signaling performance, the following general board design guidelines must. pF/cm pF/inch: T pd (Propagation delay time): psec/cm. Differential impedance refers to the inductive and capacitive impedance found between two differential traces and equals the ratio of voltage to current on the differential pair. Attenuation figure of merit: 0. The official I2C specification (page 9) states that a voltage is not considered “logic high” until it reaches 70% of V DD. 39 symmetric stripline pcb transmission lines 12. T= Experimental temperature. First, we would like to know the critical length for a USB signal being routed on a typical 2-layer PCB. PCB trace length matching is crucial for high frequency synchronous signals. Now that we understand pulse rise time (0 to 3. In terms of maximum trace length vs. They all have different frequencies of response (ranges are approximate): • 0 to approximately 30 KHz -Power supply response (varies considerably) • 70 Hz - approximately 40 KHz Bulk power supply capacitors (works with. 1. W = Trace width in inches (example: a 5-mil, i. A PCB design package that incorporates a propagation delay calculator as part of your design rules makes it easy to compensate for propagation delay, allowing you to focus on routing and signal integrity, rather than manually adjusting traces and calculating tolerances. A picosecond is 1 x 10^-12 seconds. Today's digital designers often work in the time domain, so they focus on tailoring the. Approximations for the impedance, delay, inductance, and capacitance of microstrips and striplines, as a function of trace geometry, are reproduced in my book, High-Speed Digital Design ISBN:0-13-395724-1. Nyquist frequency of 240 MHz of less than 0. More exotic dielectrics (like teflon, etc) can be quite different. The parasitic inductance that resides along a PCB trace increases the impact of any voltage spike induced by switching power supplies. 005” trace for 50 ohms) Component: Copper Traces Purpose: Interconnect two or more points Problem: Inductance and Capacitance x = length of trace (cm) w = width of trace (cm) h = height of trace (cm) t = thickness of trace (cm) e r = PCB Permeability 0. A PCB impedance calculator uses field solvers to accurately approximate impedance values. 4 should include whatever lot or panel identifi-cation is available for the substrate laminate being evaluated. R is the series resistance per unit length (Ω/m) L is the series inductance (H/m). 3. A picosecond is 1 x 10^-12 seconds. 2 PCB Stack-up and Trace Impedance. " Refer to the design requirements or schematics of the PCB. 26 3. Second choice: You can model a transmission line with a sequence of pi or T sections. Where T is the board thickness and H is the separation between traces. So it should be possible for the velocity to change without the characteristic impedance changing, but. Online calculators will generally use Wadell's equations to determine the transmission line impedance numerically. Even though these conductors may have a different DC voltage, their high frequency impedance isFor the stripline I’ve simulated above, this would equate to 1. If the rise/fall time (based on 10% to 90%) of the signal is shorter than six times the trace delay, then it’s called a high-speed signal. Megtron 6 is manufactured with 100% CAF resistant Nittobo glass Laminate thicknesses published measure the laminate base material without the metal cladding. 425 inches. 0035 cm. The difference between the speed of a wave traveling in free space versus a PCB will cause a delay between the two signals, usually referred to as propagation delay (T d). Perhaps the most common type of transmission line is the coax. 9 System. , power and/or GND). 045 inches. 44 x A0. PCB dielectric substrate is composed of woven fiber-glass bound together with epoxy resin. e. Time Delay (ps) Inspector Adolph Judgement PASS Fail Wait MRB-A-_____ Approval Alex Testing Date 2020/11/11 MFG Date Code xxxx Timing Delay Spec. Measurements of S-parameters. Again, PCB routing and signal integrity matter most here. Part of a 1984 Sinclair ZX Spectrum computer board, a printed circuit board, showing the conductive traces, the through-hole paths to the other surface, and some electronic components mounted using through-hole mounting. 2 volts (per DIMM) instead of the 1. The Usual High Speed PCB Layout Rules. CBTU02044 also brings in extra insertion loss to the system. Insertion Loss. 0 dielectric would have a delay of ~270 ps. 1. Printed circuit board of a DVD player. Refer to PCB design requirements or schematics. Terminate the transmission line in its characteristic impedance when the one-way propagation delay of the PCB track is equal to or greater than one-half the applied signal. 5. 8 ns Input maximum delay = t coIt is the function of the dielectric constant (Er) and the trace structure. 9 to 4. ) In this example, the line is 12” or about 30 cm long. Capacitance = ϵ ∗ Area/DielectricThickness C a p a c i t a n c e = ϵ ∗ A r e a / D i e l e c t r i c T h i c k n e s s. The characteristic impedance of your microstrips is determined by the trace width for a given layer stackup. Ideally, though, your daughter’s hair isn’t causing short-circuiting of electronics or small fires to spark up. Why FR4 Dispersion Matters. The EZ5 material measured at 54% of the baseline material, A1X. The tool will use 0 as the minimum trace delay if left blank which will lead to wrong Board Skew Parameter calculations. 8. The metric hole examples areMIG 7 Series includes specific trace matching requirements between CK/Addr, DQ/DQS and CK/DQS. “amplitude” by selecting the delay tune type then select the track and move the mouse upwards. Step 3B: Input the trace lengths per byte for DDR CK and DQS. 8dB/inch o Skip-layer STL: 1. The propagation delay (tpd) is the time delay through the transmission line per unit length and is a function of the natural impedance and characteristic capacitance. 33x10-9 seconds /meter or 3. and the cable's distributed capacitance per unit length, C, Figure 2 displays this relationship graphically. This graph has been extracted based the assumption that W=5 mil. The MCU itself has rather a high number of high speed interfaces all of which suppose to be used according to the specifications. This delay will roughly increase with the capacitance. 2, or 3. 5ns. 23 nH per inch. DQ and DMI traces are recommended to be controlled to ~40Ω 4. 0 x 1. 15 um package trace length for M_DQ[18] trace with delay 44. Sample 4-Layer PCB StackupFind the trace delay, or "DLY," in pico seconds or "ps" per inch. berkeman said: A ballpark figure for a PCB trace is about c/1. It is primarily used in the PCB industry to refer to signal speed, while integrated circuit designers use the same term to refer to the time required for a logic state to toggle from an input to an output. 2. 2. Z0,air Z 0, a i r = characteristic impedance of air. Just as a sanity check, we can quickly calculate the total inductance of a trace. Total loop inductance/length in 50 Ohm transmission lines. 1. To ensure timing alignment for all channels per port, both the substrate trace length plus the PCB trace length for each signal must be matched to meet the trace length skew tolerance for all signals within the clock domain. At 1. Controlled differential impedance starts with characteristic impedance. Coax Impedance (Transmission Line) Calculator. 10. A 0. Propagation delay per unit length;. The idea is to ensure that all signals arrive within some constrained timing mismatch. Let's take another case, a differential line. Vendor may adjust trace widths, trace spacings and dielectric thickness as required. It is not necessary to match the lengths of the TXPCB Trace Impedance Calculator; stripline; Electromagnetic Compatibility Laboratory. The thermal resistance of this foil is also 70 degree Centigrade per square, ignoring the holes and the etched gaps between the squares. 3MHz. All specified delay matching requirements include PCB trace delays, different layer propagation velocity variance, and. Stripline Layout Propagation Delay. ½ of the total time the signal takes to travel along the trace) then you need to consider your PCB as a high-speed circuitTable 6-4 in IPC-2221 demonstrates the relationship between copper foil cross-sectional area, temperature rise and maximum current carrying capacity among external conductors and internal conductors. All of these changes mean that the PCB designers must reassess their design approach for the implementation of DDR4. R. 0 and frequencies up to 20 GHz. 5 ps/mm and the dielectric constant is 3. ) of FR4 PCB trace (dielectric constant Er = 4. CBTL04083A/B has −1. The final result is a much improved S-parameter data set with unwanted resonance removed, allowing the PCB trace or cable loss to be determined. 2 PCB Stack-up and Trace Impedance. A copper Thickness of 1 oz/ft^2 = 0. Figure 7. 031”) trace on 0. In this example, the delay difference between the P and N legs as well as the measured trace lengths end-to-end are the same in the layout tool. Signal skew occurs in a group of signals when there are delay mismatches. 75. On PCB transmission lines, tpd is given by: Propagation delay in PCB transmission lines For example, a 1-inch trace can introduce an approximate 5. • Signal traces should not be run such that they cross a plane split. Usually, the. The thick. Use wider design rules when narrow traces and spacing aren't required. 4000 Enterprise Drive, Rolla, MO 65401 (573) 341-4139. ) These traces come from an MPSoC (BGA) with TX/RX pairs at 100 Ω impedance. Zo is 20 millohms. In most of the cases DDR2 and its previous classes follow the T-topology routing. 06 meters. frequency can be reduced to a single metric. For buried traces, such as stripline traces, the return path conductor might actually be two planes, one above, and one below. 1. e. A typical value for ER of FRC4 PCB material is 4. Minimum CAN Device Spacing Load capacitance includes contributions from the CAN transceiver bus pins, connector contacts, printed-circuit board traces, protection devices, and any other physical connections as long as theCable/PCB trace 5 Delay per meter. To achieve this, you may have to put small sections of trace tuning into the shorter line to equalize them. Component: Copper Traces Purpose: Interconnect two or more points Problem: Inductance and Capacitance x = length of trace (cm) w = width of trace (cm) h = height of trace (cm) t = thickness of trace (cm) e r = PCB Permeability 0. Multiple differential pairs routed in parallel. Rule of Thumb #5: Capacitance per length of 50 Ohm transmission lines in FR4. PCB trace as shown in Figure 12. 41] (Section 2. The calculator is set up to handle an asymmetric arrangement, where traces are not centrally located in the PCB layer stack. 031”) trace on 0. delay, it comes down to a question of how much delay your circuits can live with. Propagation Delay The propagation delay of the signal is the time it takes for the signal to travel a specific distance. 01 inch) trace on a PCB can carry approximately 0. 39 symmetric stripline pcb transmission lines 12. 8pF per cm ˜ 10nH and 2. 38 some microstrip guidelines 12. To keep a good high-speed signal quality from driver to receiver on a PCB is not an easy task for designers. Table 1. 5 ns. However, there are techniques to reduce the spacing for both dc and ac. xxx Differential Pair Spec. NOTE: DP83867 allows adjustment of RGMII delay from 0 ns to 4 ns in 0. 5 dB 14-inch on low-loss PCB material Up to 0. What is the voltage at source at. D = delay in ps/inch The delay of FR4 material is 180 ps/inch. 5 ohms peak to peak. Keep traces short and direct, which is easiest. What is the characteristic impedance of twisted pair cables? 100 ohms. That’s Ohms per square, without any other dimension; a square of copper two millimeters on a side has the same resistance as a square of copper ten millimeters on a side. 1 Flight Delay and Skew Advantages to Specifying Timing Specifications via PCB Routing Rules Another particularly nasty negative result is one which reflects that the system designer's attempt was to design an. Furthermore, it achieves these increases in performance in spite of using less power; 1. The stripline impedance calculator provided below is useful for gaining an initial estimate of trace impedance for striplines. Those familiar with high-speed design know that trace geometry, trace location, and board substrate all affect signal speed, impedance matching, and propagation delay. Capacitance per unit length is proportional to trace width (neglecting edge effects). Voltage Drop is. The source for formulas used in this calculator. Assume trace delay, pin capacitance, and rise/fall time differences between data and clock are negligible. Electric signals travel 1 inch in 6 ns on an Fr4 copper trace. Brad - November 15, 2007 Mike, In PCB Designs we use another term propogation speed and measure it in terms of picosecond per inch. The delay of this cable is 1. 0 will make the migration at the touch of a button. 2. 3 LVDS Traces • As shown in Figure 1, traces should be 100-Ω(±5%) differential impedance of differential microstrip or differential stripline. A thicker trace will have lower inductance per unit length. )No Plated Holes Needed,)Can Narrow Trace to Match Component Leads. The propagation delay depends on the dielectric constant, it is proportional to the square root of it. 7563 mm (~30 mils). Speci-mens from 3. trace width. Figure 5-1 shows an example PCB stackup with trace routing on layer 1, ground on layer 2, power on layer 3 and trace routing on layer 4. However, usually the effect of the excessive load capacitance will be to slow the voltage transitions on the trace. e. However, I have a bit of a length mismatch between the TX+/TX- and RX+/RX- pairs (about 5mm). (138 pF/m) yields 178. To make the math easier, the value is rounded up to 300,000,000 m/s (or. 2. Stripline Layout Propagation Delay. PCB traces. Here, I’ve taken the real value of γ as this tells us the. Simply enter your required temperature rise limits and operating current (RMS). 5. 427This paper presents a methodology for board-level timing analysis, concentrating on two specific areas: pre-route (preliminary design) and post-route (PCB design). 5. Most of this time is taken up by the edge rate of the driver. The calculated FPGA and HardCopy ASIC timing constraints are as follows: Output maximum delay = t su of external register = 1. Rule of Thumb #1: Bandwidth of a signal from its rise time. GEGCalculators. Matched lengths minimize delay differences, avoiding an increase in common mode noise and increased EMI. measured lot to lot loss variation to be ~±0. Figure 5 (not to scale) shows cross-sections of typical wire geometries. Convert the length of the trace to delay by using a lumped per inch number. Using the above rule strictly, termination would be appropriate whenever the signal rise time is < ~500 ps. Managing all of these can be done manually. In vacuum or air, it equals 85 picoseconds/inch (ps/in). the min delay of STARTUP), the max delay of the data path and the board routing delay Similarly, T hold analysis should be done by taking into account the max delay on SCK (i. The dielectric constant (and thus the refractive index) of a material is a function of a traveling electromagnetic wave’s oscillation frequency. PCB Trace Considerations • Avoid using 90 degree angles in the high speed data traces. I will plan on releasing a web calculator for this in the future. How to calculate trace delay? Simple (not recommended): Measure the physical trace length (in mils or mm) in a layout tool. )May Need to Strap Grounds together on Either Side of Trace, every 1/20th Wavelength. Beware though, large copper areas have extra capacitance, so if you have a high dv/dt node, like the switching node of a DC-DC. Each S-parameter (Sij) has a real magnitude and a phase in the complex part. Factors that determine the PCB impedance Z0 value for a better RL performance are: Picking the PCB impedance Z0 that gives the minimum impedance fluctuation (discontinuity) with all other elements of the channel is the key. 3. a. Figure 2. = Most PCB vendors will size traces for you You just tell them Z0 L0 is inductance per unit length C0 is capacitance per unit length. 32 f \ tan(\delta) \sqrt{\epsilon_r}\] Equation 1. 031”) thick PCB (FR-4) has: ˜ 4nH and 0. Figure 78 shows the propagation delay versus the dielectric constant for microstrip and stripline traces. 44A0. Trace Width: 0. The CPU then writes all other PHYs with the value + + t2 tp (optional trace delay compensation for load/save signal) + fixed_load_latency, and then sets the load bit in each PHY. Previous: Rule of Thumb. To quickly check the quality of PCB design, consider the following: 1. It is important to precisely configure the layers and materials in the stackup to support high speed and RF microstrip and stripline routing. PCB-RULER-ND: Metric Side Rev 1 (March 2016) 12 inch (~30.